The present invention relates to a current digital-analog converter. It can be applied especially to digital-analog sigma-delta type converters.
The present development of technologies is tending to shift the boundary between digital technologies and analog technologies in order to reduce the analog part to the maximum extent. This trend is designed especially to simplify the hardware architecture of systems by performing most of the functions in digital techniques while at the same time reducing manufacturing costs. A major consequence of this development is the huge increase in the constraints carried over to the analog-digital or digital-analog conversion part, since ultimately the converter is at the end or almost at the end of the processing chain. The converters must therefore comply with increasingly demanding performance requirements.
With regard to digital-analog converters, there are several types. Among these different types, the sigma-delta type converters are of considerable interest since they work with only one conversion bit.
In sigma-delta type converters, the binary signal encoded on N bits and sampled at a given frequency Fs is converted by digital means into an over-sampled one-bit signal, namely a signal sampled at a far higher frequency F""s=MxFs. This signal is then converted into an analog signal by means of a one-bit digital-analog converter and a lowpass filter placed at output of the converter.
There are many known ways of making this type of digital-analog converter. It is possible to make a voltage converter, i.e. a converter where either a positive voltage at a potential +Vref or a negative voltage at a potential xe2x88x92Vref is sent at output, depending on the state of the binary signal. This structure however is limited in particular to a distortion level of about 60 dB and is sensitive to the instabilities, generally known as xe2x80x9cJitterxe2x80x9d, in the reference clock. This jitter in particular prompts a parasite noise at the output of the converter.
Current converters are also made. In this case, either a positive current with a value +Iref or a negative current with a value xe2x88x92Iref is sent, depending on the state of the binary signal. These converters give very high distortion performance characteristics. However, they remain sensitive to the jitter of the clock.
There are also known ways of making switched-capacitor converters that are insensitive to the jitter of the clocks but they require very fast amplifiers to obtain efficient distortion performance levels.
An aim of the invention is to enable the making of a converter that ensures a high level of distortion and is insensitive to the jitter of the reference clock.
To this end, an object of the invention is a digital-analog current converter receiving, at input, a succession of bits of a binary signal and delivering, at output, sampled by a clock signal, a positive or negative current depending on the state of the input bit, wherein the converter comprises at least one circuit to control the build-up time of the output current of the converter, the build-up time being controlled by the charging of a capacitor by a constant current up to a reference voltage.
In a second embodiment, the circuit to control the build-up time of the output current comprises at least two reference voltages, the capacitor being charged and then discharged between these two voltages, the build-up time of the output current then being the sum of the time taken to charge the capacitor and the time taken to discharge the capacitor. An advantage of this embodiment is that it can be used to obtain high electrical efficiency.
In a third embodiment, the charging and discharging current of the capacitor is sent directly into the output load of the converter by means of selector switches and current mirrors. Two capacitors are used and are they are charged and discharged. While one of the capacitors gets charged, the other gets discharged. One advantage of this embodiment is that it can be used to overcome the current noise of the converter.